Memory system architectures are currently designed combining a variety of memory devices such as semiconductor memory devices (e.g., dynamic RAM, static RAM, flash memory), magnetic discs, and the like. This means that it is very difficult to support all memory spaces of, for example, a personal computer, by using only one type of memory device.
In the field of semiconductor memory devices, the improvements in device density, high-speed read/write operation, access time, low power consumption, etc. have long since been required but have faced inevitable technology limitations.
One solution to such limitations has been the development of ferroelectric memory devices. Ferroelectric memory devices which retain data even when powered off, have been realized through the use of a ferroelectric material such as lead zirconate titanate (PZT). PZT has desirable characteristics including the ability to exhibit hysteresis. Several examples of ferroelectric memory techniques have been disclosed in several published articles. One such published article appeared in the IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1171.about.1175, October 1988, and is entitled "An Experimental 512-bit Nonvolatile Memory with Ferroelectric Storage Cell." Another article appeared in Electronics, pp. 32, Feb. 4, 1998 and is entitled "New Challenger: The Ferroelectric Ram." Both of the above-mentioned published articles are incorporated herein by reference.
As is well known in this art, ferroelectric material has spontaneous polarization characteristics. The direction of the polarization is controlled by the direction of an electric field. Typical ferroelectric materials include the ABO.sub.3 type of the PbZrO.sub.3 molecule. A metal atom, i.e., zirconium (Zr) which is positioned at the center of the PbZrO.sub.3 molecule has two stable state points according to the polarization direction of the applied electric field. Thus, the ferroelectric material exhibits hysteresis characteristics.
Ferroelectric Random Access Memory (FRAM) devices take advantage of the hysteresis characteristics of the ferroelectric material. FRAMs have non-volatile memory storage characteristics by corresponding the degree of polarization to binary data. FRAMs are capable of performing very fast read/write operations by taking advantage of the very fast inversing speed of polarization.
A ferroelectric memory cell will be described hereinafter based on the above-mentioned published articles. FIG. 1 shows the circuit of a ferroelectric memory cell. The ferroelectric memory cell consists of a charge transfer transistor T.sub.F and a ferroelectric capacitor C.sub.F. The ferroelectric memory cell shown in FIG. 1 is suitable for large scale capacity memory devices. In each ferroelectric memory cell, the capacitor C.sub.F has a ferroelectric material inserted between both electrodes. One of the two electrodes, i.e., one plate electrode, is set to a predetermined middle voltage between the two voltages corresponding to a logic "1" and a logic "0." The charge transfer transistor T.sub.F includes a channel and a gate. The channel of the charge transfer transistor T.sub.F is connected between the other electrodes of the two electrodes of the capacitor C.sub.F and the bit line BL. The gate of the charge transfer transistor T.sub.F is connected to the word line WL. The charge transfer transistors included in the FRAM are fabricated using well-known CMOS fabrication techniques.
FIG. 2 is a graph of the hysteresis I-V switching loop of the prior art ferroelectric capacitor. In this graph, the abscissa indicates the potential difference between the electrodes of the ferroelectric capacitor, i.e., the voltage between both ends of the capacitor. The ordinate of the graph indicates the amount of charge induced in the surface of ferroelectric material according to the spontaneous polarization, i.e., degree of polarization in micro-coulombs per centimeter squared (.mu.C/cm.sup.2).
As shown in FIG. 2, if no electric field is applied to the ferroelectric material with a zero voltage applied thereto, polarization does not occur. When a voltage is increased in the positive direction of the graph, the degree of polarization is increased from zero up to a point "A" inside the positive charge polarization domain. At the point "A", all the domains are polarized in one direction and the degree of polarization is maximized. In this case, the degree of polarization, i.e., the amount of charge contained in the ferroelectric material is equal to Qs and the applied voltage is equal to the power supply voltage Vcc. Once at point A, even if the voltage is lowered again to zero volts, the degree of polarization is not reduced to zero, but remains at a point "B". The amount of charge in the ferroelectric material, i.e., the remaining degree of polarization is equal to Qr.
Next, if the voltage is increased in a negative direction of the graph, the degree of polarization is changed from the point "B" to a point "C" inside the negative charge polarization domain, as shown by curve 21 of FIG. 2. At point "C", all domains of the ferroelectric material are polarized in a reversed direction with respect to the polarization direction at the point "A". The degree of polarization is then equal to -Qs and the applied voltage is equal to the power supply voltage -Vcc. Once at point C, even if the voltage is lowered again to zero volts, the degree of polarization is not reduced to zero, but remains at a point "D". The remaining degree of polarization is equal to -Qr. If the voltage is increased once more in the positive direction, the degree of polarization is changed from the point "D" to the point "A".
Thus, if a voltage causing an electric field is applied to the ferroelectric capacitor which includes a ferroelectric material inserted between the two electrodes, even though the electrodes are set to a floating state, the polarization direction according to the spontaneous polarization can be continuously maintained. Because of the spontaneous polarization, the surface charges of the ferroelectric material are not spontaneously dissipated due to leakage. If the voltage is not applied to change the degree of polarization to zero, the polarization direction continues to be maintained.
Read and write operations of the FRAM can be carried out by polarization reversion. The speed of the read and write operations are determined by the time it takes to reverse the polarization of the FRAM cell. The speed of polarization reversion of the ferroelectric capacitor is determined by a variety of factors including the capacitor area, the thickness of ferroelectric thin film, and the applied voltage. The unit of the speed of polarization reversion is typically microseconds (.mu.s). Thus, FRAM devices operate faster than electrically erasable and programmable read only memory (EEPROM) devices or flash memory devices.
The read and write operation of the prior art FRAM functions as follows. A binary data signal corresponds to points "B" and "D" of the hysteresis loop shown in FIG. 2. Logical "1" corresponds to point "B" and logical "0" corresponds to point "D". Turning again to FIG. 1, at an initial stage of the read and write operation of the FRAM, data stored in memory cells is sensed by a sensing circuit. During the sensing operation, a zero voltage or ground voltage Vss is applied to the selected bit line BL. The charge transfer transistor T.sub.F is then turned on by the selected word line WL so that zero voltage on the bit line BL is applied to one electrode of the ferroelectric capacitor C.sub.F and a pulse of power supply Vcc is applied to the other electrode thereof. At this time, if logic "1" data is stored in the capacitor C.sub.F, the degree of polarization of the capacitor C.sub.F is varied from the point "B" to the point "D" via the point "C". As a result, a charge dQ is transmitted from the capacitor C.sub.F to the bit line BL increasing the voltage on the bit line BL.
Conversely, if logic "0" data is stored in the capacitor C.sub.F, the degree of polarization of the capacitor C.sub.F is varied from point "D" to point "C" and returns to point "D". In this case, the voltage on the bit line BL is not changed. The bit line voltage is compared with a reference voltage REF by means of a well-known sensing circuit (not shown). If the bit line voltage is more than the reference voltage REF, it is increased up to an operational voltage level i.e., the power supply Vcc level. If the bit line voltage is less than the reference voltage REF, the bit line voltage is lowered again to zero or ground voltage Vss.
The data write or read operation of the prior art FRAM begins after the completion of the data sensing operation. During the write operation, the voltage on the data line is delivered to the bit line BL by means of a well-known column decoder (not shown). After lapse of a predetermined time, a pulse is applied to the ferroelectric capacitor C.sub.F. The degree of polarization of the ferroelectric capacitor C.sub.F is moved from the point "B" to the point "D" so that the logic "1" or "0" data is written in to the memory cell.
If such a sensing operation is carried out once with respect to the cell which stores logic "1" data (the degree of polarization of Qr is at the point "B") or if a pulse is applied once to the ferroelectric capacitor C.sub.F which stores logic "1" data, the stored data is changed into logic "0" data (the degree of polarization of -Qr at the point "D") because of the hysteresis characteristics of the ferroelectric capacitor C.sub.F. Therefore, before the completion of the write operation, it is necessary to allow for the recovery of the ferroelectric capacitor C.sub.F of the non-selected memory cell to an initial state. This data recovery is called "rewrite" or "restore". The power supply voltage Vcc of the pulse is applied once more to the ferroelectric capacitor C.sub.F of the memory cell whose sensing operation is completed. Thus, the degree of polarization of the ferroelectric capacitor C.sub.F of the non-selected memory cell is recovered from -Qr (logic "0" ) at point "D" to Qr (logic "1") at point "B".
Next, during the read operation of the FRAM, data on the bit line BL obtained by the data sensing operation is directly delivered to external circuitry. Even during the read operation, if the sensing operation is carried out once with respect to the cell which stores logic "1" data, the data stored in the ferroelectric capacitor C.sub.F is changed into logic "0" data Therefore, before the completion of the read operation, the power supply voltage Vcc of the pulse is applied once more to the ferroelectric capacitor C.sub.F of the memory cell whose sensing operation is completed. Thus, the degree of polarization of the ferroelectric capacitor C.sub.F read is recovered from -Qr to Qr at point "B".
In the prior art FRAM having the above-described structure, the "domain switching" phenomenon causes the polarization of the ferroelectric capacitor to change during one write/read cycle. Where the write/read cycle is repeated, the permanent degree of polarization of ferroelectric material is reduced due to fatigue. Fatigue reduces the endurance of FRAMs. Also, since the cell data sensed during the sensing operation is amplified to an operational power supply voltage Vcc, a voltage higher than the operational power supply voltage Vcc must be supplied to the word line in order to maintain proper operation. Thus, the prior art FRAM requires an additional booster circuit which increases the device's power consumption.
Accordingly, a need remains for a FRAM with improved endurance and lower power consumption.